Akash Levy

After the passage of the US National Quantum Initiative Act in December 2018 [1], the National Science Foundation (NSF) and the Office of Science and Technology Policy (OSTP) recently assembled an interagency working group and conducted a workshop titled "Key Concepts for Future Quantum Information Science Learners" that focused on identifying core concepts for future curricular and educator activities [2-3] to help pre-college students engage with quantum information science (QIS). Helping… Show more

After the passage of the US National Quantum Initiative Act in December 2018 [1], the National Science Foundation (NSF) and the Office of Science and Technology Policy (OSTP) recently assembled an interagency working group and conducted a workshop titled "Key Concepts for Future Quantum Information Science Learners" that focused on identifying core concepts for future curricular and educator activities [2-3] to help pre-college students engage with quantum information science (QIS). Helping pre-college students learn these key concepts in QIS is an effective approach to introducing them to the Second Quantum Revolution and inspiring them to become future contributors in the growing field of quantum information science and technology as leaders in areas related to quantum computing, communication and sensing. This paper is a call to pre-college educators to contemplate including QIS concepts into their existing courses at appropriate levels and get involved in the development of curricular materials suitable for their students. Also, research by Schwartz et al. [4] has shown that compared to the case in which students are told physics concepts and formulas and asked to use them to practice, when students are given an opportunity to invent with contrasting cases, they exhibited higher order learning and were able to transfer their learning more frequently to unrelated topics. Therefore, we illustrate a pedagogical approach that contrasts the classical and quantum concepts so that educators could adapt them for their students in their lesson plans to help them learn the differences between key concepts in quantum and classical contexts. Show less

In this paper, we propose the use of multi-pole nanoelectromechanical (NEM) relays for routing multi-bit signals within a coarse-grained reconfigurable array (CGRA). We describe a CMOS-compatible multi-pole relay design that can be integrated in 3-D and improves area utilization by 40% over a prior design. Additionally, we demonstrate a method for placing multiple contacts on a relay that can reduce contact resistance variation by 40xover a naive placement strategy. We then show a methodology… Show more

In this paper, we propose the use of multi-pole nanoelectromechanical (NEM) relays for routing multi-bit signals within a coarse-grained reconfigurable array (CGRA). We describe a CMOS-compatible multi-pole relay design that can be integrated in 3-D and improves area utilization by 40% over a prior design. Additionally, we demonstrate a method for placing multiple contacts on a relay that can reduce contact resistance variation by 40xover a naive placement strategy. We then show a methodology for integrating these relays into an industry-standard digital design flow. Using our multi-pole relay design, we perform post-layout simulation of a processing element (PE) tile within a hybrid CMOS-NEMS CGRA in 40 nm technology. We achieve up to 19% lower area and 10% lower power at iso-delay, compared to a CMOS-only PE tile. The results show a way to bridge the performance gap between programmable logic devices (such as CGRAs) and application-specific integrated circuits using NEMS technology. Show less

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with SAPIENS, a resistive RAM (RRAM) based non-volatile associative memory (AM) chip that serves as the backend for memory-augmented neural networks. The 64-kbit fully-integrated RRAM-CMOS AM chip performs long-term feature embedding and retrieval, demonstrated on a 32-way one-shot learning task on the Omniglot… Show more

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with SAPIENS, a resistive RAM (RRAM) based non-volatile associative memory (AM) chip that serves as the backend for memory-augmented neural networks. The 64-kbit fully-integrated RRAM-CMOS AM chip performs long-term feature embedding and retrieval, demonstrated on a 32-way one-shot learning task on the Omniglot dataset. Using only one example per class for 32 unseen classes during on-chip learning, SAPIENS achieves 79% measured inference accuracy on Omniglot, comparable to edge software model accuracy using 5-level quantization (82%). It achieves an energy-efficiency of 118 GOPS/W at 200 MHz for in-memory L1 distance computation and prediction. Multi-bank measurements on the same chip show that increasing the capacity from 3 banks (24 kb) to 8 banks (64 kb) improves the chip accuracy from 73.5% to 79%, while minimizing the accuracy excursion due to bank-to-bank variability. Show less

HfO₂-based Resistive RAM (RRAM) is an emerging non-volatile memory technology that has recently been shown capable of storing multiple bits-per-cell. The energy/delay costs of an RRAM write operation are dependent on the number of pulses required for RRAM programming. The pulse count is often large when existing programming approaches are used for multiple bits-per-cell RRAM, especially when resistance ranges are allocated to account for retention. We present a new technique, Range-Dependent… Show more

HfO₂-based Resistive RAM (RRAM) is an emerging non-volatile memory technology that has recently been shown capable of storing multiple bits-per-cell. The energy/delay costs of an RRAM write operation are dependent on the number of pulses required for RRAM programming. The pulse count is often large when existing programming approaches are used for multiple bits-per-cell RRAM, especially when resistance ranges are allocated to account for retention. We present a new technique, Range-Dependent Adaptive Resistance Tuning (RADAR), for fast and energy-efficient programming of multiple bits-per-cell RRAM arrays, using a combination of coarse- and fine-grained RRAM resistance tuning. Experimental data is collected on 16K cells from two 1Megacell (1M physical cells) 1T1R HfO₂-based RRAM arrays fabricated in a 130-nm CMOS process. RADAR reduces the programming pulse count by 2.4X (for both uncycled cells and cells that have undergone 8K cycles) on average over existing programming techniques tested on the same RRAM arrays, with the same bit error rate targets. Show less

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning using a 2T-2R resistive RAM (RRAM) non-volatile associative memory (AM) as the backend of memory-augmented neural networks (MANNs). The 64-kbit fully integrated RRAM-CMOS AM core (0.2 mm² at 40 nm node) enables long-term feature embedding and retrieval, demonstrated in a challenging 32-way one-shot learning task… Show more

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning using a 2T-2R resistive RAM (RRAM) non-volatile associative memory (AM) as the backend of memory-augmented neural networks (MANNs). The 64-kbit fully integrated RRAM-CMOS AM core (0.2 mm² at 40 nm node) enables long-term feature embedding and retrieval, demonstrated in a challenging 32-way one-shot learning task using Omniglot dataset. Using only one example per class for 32 unseen classes during on-chip learning, our AM chip achieves ~72% measured inference accuracy on Omniglot as the first chip accuracy report compared to software accuracy (~82%), while reaching 118 GOPS/W for in-memory L1 distance computation and prediction. Show less

Two-terminal Resistive Random-Access Memory (2T-RRAM) devices have been researched extensively for high density memory and neuromorphic computing applications. Recently, a three-terminal variant (3T-RRAM) of this device family has been investigated experimentally, which, by separating the read and write terminals, seeks to enable efficient resistive state tuning and flexible neuromorphic architectures. State switching in these devices has been theorized to occur via a combination of (1)… Show more

Two-terminal Resistive Random-Access Memory (2T-RRAM) devices have been researched extensively for high density memory and neuromorphic computing applications. Recently, a three-terminal variant (3T-RRAM) of this device family has been investigated experimentally, which, by separating the read and write terminals, seeks to enable efficient resistive state tuning and flexible neuromorphic architectures. State switching in these devices has been theorized to occur via a combination of (1) field-driven oxygen vacancy migration and (2) electron transport based on trap-assisted-tunneling. We developed a Monte Carlo simulator for 3T-RRAMs which captures these two mechanisms, demonstrating agreement between its predictions and published experimental results. Using this simulator, we studied the response of 2T- and 3T-RRAMs under pulsed operation and showed that 3T-RRAMs have the potential to deliver superior inference accuracy in neuromorphic applications. Show less

We present the first demonstration of 1T4R Resistive RAM (RRAM) array storing two bits per RRAM cell. Our HfO2-based RRAM is built using a logic foundry technology that is fully compatible with the CMOS back-end process. We present a new approach to program RRAM cells using gradual SET/RESET pulses while minimizing disturbances on adjacent cells (belonging to the same 1T4R RRAM structure) – this new approach makes our multiple-bits-per-cell 1T4R RRAM array demonstration possible. We report over… Show more

We present the first demonstration of 1T4R Resistive RAM (RRAM) array storing two bits per RRAM cell. Our HfO2-based RRAM is built using a logic foundry technology that is fully compatible with the CMOS back-end process. We present a new approach to program RRAM cells using gradual SET/RESET pulses while minimizing disturbances on adjacent cells (belonging to the same 1T4R RRAM structure) – this new approach makes our multiple-bits-per-cell 1T4R RRAM array demonstration possible. We report over 1E6 cycles of endurance and a projected 10-year retention at 120°C. Using measured data from our 2 bits-per-cell 1T4R RRAM array, we analyze multiple deep learning applications and demonstrate high degrees of inference accuracy (within 0.01% of ideal values). Show less

Content Delivery Networks (CDNs) are distributed overlay networks that deliver content to end users on behalf of origin websites. They have generally been treated by both origin websites and end users as trusted entities—as a result, there has been little study on potential privacy threats that arise from their widespread usage. In this thesis, we consider privacy threats posed by CDNs that have access to a large set of user browsing information. We examine CDN usage in top websites and discuss… Show more

Content Delivery Networks (CDNs) are distributed overlay networks that deliver content to end users on behalf of origin websites. They have generally been treated by both origin websites and end users as trusted entities—as a result, there has been little study on potential privacy threats that arise from their widespread usage. In this thesis, we consider privacy threats posed by CDNs that have access to a large set of user browsing information. We examine CDN usage in top websites and discuss what inferences the most popular CDNs might be able to make about end users based on the quantity and nature of the content they deliver. Show less

Oxide nanoelectronics is a rapidly growing field which seeks to develop novel materials with multifunctional behavior at nanoscale dimensions. Here are described explicit step-by-step procedures for creating LaAlO₃/SrTiO₃ nanostructures using a reversible conductive atomic force microscopy technique. The processing steps for creating electrical contacts to the LaAlO₃/SrTiO₃ interface are first described. Conductive nanostructures are created by applying voltages to a conductive atomic force… Show more

Oxide nanoelectronics is a rapidly growing field which seeks to develop novel materials with multifunctional behavior at nanoscale dimensions. Here are described explicit step-by-step procedures for creating LaAlO₃/SrTiO₃ nanostructures using a reversible conductive atomic force microscopy technique. The processing steps for creating electrical contacts to the LaAlO₃/SrTiO₃ interface are first described. Conductive nanostructures are created by applying voltages to a conductive atomic force microscope tip and locally switching the LaAlO₃/SrTiO₃ interface to a conductive state. A versatile nanolithography toolkit has been developed expressly for the purpose. Then, these nanostructures are placed in a cryostat and transport measurements are performed. The procedures described here should be useful to others wishing to conduct research in oxide nanoelectronics. Show less

A two dimensional electron gas has recently been demonstrated at the interface between amorphous Al₂O₃ and TiO₂-terminated SrTiO₃ by atomic layer deposition (ALO/STO). Similar to LaAlO₃/SrTiO₃ heterostructures, when the ALO thickness exceeds a critical thickness, the interface becomes conducting. By using a conducting atomic force microscope tip to control the metal-insulator transition at nanoscale dimensions, we are able to create nanostructures with exceptionally high mobility… Show more

A two dimensional electron gas has recently been demonstrated at the interface between amorphous Al₂O₃ and TiO₂-terminated SrTiO₃ by atomic layer deposition (ALO/STO). Similar to LaAlO₃/SrTiO₃ heterostructures, when the ALO thickness exceeds a critical thickness, the interface becomes conducting. By using a conducting atomic force microscope tip to control the metal-insulator transition at nanoscale dimensions, we are able to create nanostructures with exceptionally high mobility. Quasi-two-dimensional written structures exhibit Shubnikov de Haas oscillations and mobilities in excess of 2,000 cm²/Vs. Furthermore, by decreasing the channel width to 10 nm width, the mobility becomes as high as 100,000 cm²/Vs. Show less