Stars
A homebrew 16-bit CPU with a homebrew Unix-like-ish operating system.
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
A FPGA friendly 32 bit RISC-V CPU implementation
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
data compression library for embedded/real-time systems
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
Getting better at Linux with 10 mini-projects.
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
UPduino 3.0: new 4 layer layout, various other improvements
A tiny Open POWER ISA softcore written in VHDL 2008
Experimental flows using nextpnr for Xilinx devices
🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
Verilog Ethernet components for FPGA implementation
Terrain rendering algorithm in less than 20 lines of code
FPGA SoC code and application example for Hackaday Supercon 2019 badge
tinyVision.ai Vision & Sensor FPGA System on Module
An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
Markdown source for Michael Abrash's Graphics Programming Black Book