Nishit K.

Changed the default round robin scheduling policy in Xinu to make it support exponential and Linux like scheduling policy where the exponential policy randomly selects a process and then checks it's probability
to run based on the probability exponential distribution.

The linux like scheduler implements Multi level feedback queue to select the process in order to eliminate the starvation problems os low priority processes and assigns goodness values to change the priority of the… Show more

Changed the default round robin scheduling policy in Xinu to make it support exponential and Linux like scheduling policy where the exponential policy randomly selects a process and then checks it's probability
to run based on the probability exponential distribution.

The linux like scheduler implements Multi level feedback queue to select the process in order to eliminate the starvation problems os low priority processes and assigns goodness values to change the priority of the processes during run time.

It also supports priority boosting feature. Show less

- Study of various methods and approach to implement issue queue based load-store synchronization (Sore sets, vectors; Sticky-Bit)
- Performance analysis on various SPEC benchmarks using Memory order violations, false dependencies, memory trap cycles and IPC.

-Performance analysis measuring Speed and Latency of embedded systems.
-Sizing analysis measuring the memory requirement by the various programs and benchmarks.
-Optimizations based on above analysis in terms of execution speed and responsiveness for faster run-times (Speed requirement) and Program size for smaller code-sizes (Memory requirement) using Linking time optimizations, SIMD instructions based on the concepts of Compilers, Microprocessor architecture and Embedded systems… Show more

-Performance analysis measuring Speed and Latency of embedded systems.
-Sizing analysis measuring the memory requirement by the various programs and benchmarks.
-Optimizations based on above analysis in terms of execution speed and responsiveness for faster run-times (Speed requirement) and Program size for smaller code-sizes (Memory requirement) using Linking time optimizations, SIMD instructions based on the concepts of Compilers, Microprocessor architecture and Embedded systems architecture. Show less

- Study of how sizes of various structures in the Microprocessor architecture such as Issue width, Fetch width, Active-list, Memory unit, Register File, Checkpoints affects the performance and parallelism.
- Effects of Memory disambiguation, Branch predictor units, Trace cache, Data cache on ILP.

Designed a simulator for an out-of-order superscalar processor based on Tomasulo’s algorithm that fetches, dispatches and issues N instructions per cycle.
Modeled dynamic scheduling mechanism to evaluate the effect of Queue size & reorder buffer size on Instructions per cycle for 2 different benchmark instruction traces in the simulator.

Designed a branch predictor simulator and used it to model bimodal, g-share and hybrid branch predictors. The simulator also included a fully associative Branch Target Buffer that stores the history of the previous branches.

Designed tanh activation unit present in the LSTM cell in Verilog HDL.
Performed gate level synthesis and netlist generation using Synopsys Design Compiler.

Designed a non-preemptive, non-prioritize scheduler that reads data from an on board Accelerometer using i2c interface. Did task scheduling by implementing Finite state machine. Reported FSM's timing analysis.
Designed same functionality using preemptive, prioritized scheduler (RTX5 real time Kernel)

Concepts covered: i2c Interface, Task scheduling algorithms: Polling, Round robin, FSM, Message queues, Software interrupts, RTOS timer, Hardware timer.

ADC sharing between Touchscreen and Buck convertor on KL25Z's development board.
USed the concept of mutexes in RTOS for safetly sharing a common resource between 2 Tasks.
Other concepts used/ implemented: Mutex, Software interrupts, ADC, Message queues, Prioritiy (RTOS).

Implemented flexible cache and memory hierarchy simulator to study performance of various memory hierarchies.
It was modeled as L1, L2 and decoupled sectored cache with Least recently used replacement policy along with Write Back Write access write policy.
Simulator outputs counts for all cache misses, hits, write backs and swaps.

Developed a fully functional bidirectional multi-hop wireless mesh network infrastructure with advanced security for the street lamp controllers for the Smart city Project.

Implemented Firmware Over the Air feature in the company's product suite to remotely update the Firmware of the end devices via IOT protocols.

Using Low power capability of the Wireless Technology (Bluetooth LE) to make an Attendance System that uses Smartphones to mark the Attendance. Making it accessible to the Institution by incorporating Wifi.