Jim Kring

Tool companies like those providing StarRC, xRC, and QRC (e.g., Synopsys, Cadence) aim to deliver accurate parasitic extraction tools, but their accuracy depends on multiple factors. These tools rely heavily on foundry-provided process data, rule decks, and technology files to model parasitics accurately. Since the tools learn and adapt based on foundry inputs (e.g., layer definitions, capacitance models), their initial accuracy can vary until calibrated with specific foundry data. In practice, the tools may not be perfectly accurate out of the box due to: Differences in foundry processes not fully captured in generic models. Evolving technology nodes requiring updates. User configuration errors or incomplete rule decks. Foundries often provide detailed documentation and validation data, and tool companies refine their algorithms based on this feedback. Thus, while the tools are not inherently inaccurate, their precision improves with foundry-specific calibration and user expertise. For critical applications, validating tool outputs against silicon measurements or foundry benchmarks is essential.

1

Magillem Connectivity by Arteris automates and simplifies the manual SoC integration process by accelerating development while improving quality and traceability. Watch the video to learn more and see how it could benefit your projects!

21

A really nice way to get your feet wet, or just have fun, creating a custom peripheral for a RISC-V processor that will be taped out. Somewhere between competition and collaboration, this cool activity will be merging everyone's submission as dedicated hardware peripherals available to Mike Bell's TinyQV processor (https://lnkd.in/e8-XACTn). Whether you want to get into Verilog and designing hardware modules, want to dig into RISC-V and see one way of multiplexing dedicated hardware extensions, or experience getting a digital design hardened and taped out on a real #ASIC, this challenge lets you do it all. Submitting an entry that gets on the chip is free :) A good overview and discussion in Matt's livestream. Or dive right into the docs at https://lnkd.in/e67c48Q6

13

Dealing with EMI issues in your flyback converter? It’s a headache no one wants, failed designs, costly rework, and endless frustration. Sure, you could try trial-and-error with your PCB layout, but who has time for that? There’s a better way. In this video, Kirsch shows you how to set up creepage and clearance rules in Allegro X to prevent arcing and meet standards like IEC and UL. No guesswork, no wasted time, just a more reliable way to meet EMI and safety standards. Watch now! https://ow.ly/urrK50XZyP8 #PCBDesign #AllegroX

1

Sagire AI is using its proprietary AI tool to radically change how embedded system software is developed, deployed, and maintained.

17

2 Comments

Here's a shoutout to Henry Ott, who wrote Partitioning and Layout of a Mixed-Signal PCB, and to Lionel Wallace, who recently shared this article. Here is the full checklist: 1. Partition your PCB with separate analog and digital sections. > Create a plan and stick with it. 2. Place components properly. > Follow the plan! 3. Straddle the partition with the A/D converters. > When the partitioning is followed, the placement of the mixed-signal components is natural. 4. Do not split the ground plane. Use one solid plane under both analog and digital sections of the board. > Never split the ground plane! 5. Route digital signals only in the digital section of the board. This applies to all layers. > See traces as components. Keep each group in its partition. 6. Route analog signals only in the analog section of the board. This applies to all layers. > As in the previous point. 7. Separate analog and digital power planes. > A dedicated power plane layer is a big advantage. 8. Do not route traces over the split in the power planes. > See the split in the power planes as a milled slot. 9. Traces that must go over the power plane plit must be on layers adjacent to the solid ground plane. > The adjacent reference plane is a big protector here. 10. Think about where and how the ground return currents are actually flowing. > Imagine how the current flows back. 11. Use routing discipline. > Take all the mentioned points as golden rules and never break them. If you want to read all of my posts, use the #thatkicadguy tag in the search field above

89

14 Comments