Abhisek Verma

Abhisek Verma

Greater Boston
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Since 2006 I've been making waves as an enthusiastic key player in the semiconductor…

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  • Switch the Gears of the UVM Register Package to Cruise through the Street Named “Register Verification”

    DVCON, 2013

    “Register verification” could seemingly be a simple task but in reality it tends to have an adverse effect on project schedules on account of factors such as changes to the RTL specification, design changes/optimizations, migration efforts from block to sub-system or system level and so on. Traditionally design houses had their own methodologies to reduce the time and effort spent in creating and maintaining register tests. The UVM register package advocates best practices like object oriented…

    “Register verification” could seemingly be a simple task but in reality it tends to have an adverse effect on project schedules on account of factors such as changes to the RTL specification, design changes/optimizations, migration efforts from block to sub-system or system level and so on. Traditionally design houses had their own methodologies to reduce the time and effort spent in creating and maintaining register tests. The UVM register package advocates best practices like object oriented abstraction, automation etc. to provide a robust platform for register verification. This package easily automates the creation of object-oriented abstract model of the registers/memories inside a design and has been adopted by a lot of users in the industry. In this paper, we present some techniques which could be used to leverage the existing package efficiently for advanced register verification. We also present an auxiliary package to exploit the abstraction levels provided by the library to ease the process of software validation which is closely tied to registers and memories in a system.

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  • Advanced Applications of Resources: How we Solved our SoC Verification Challenges with UVM Configuration Mechanism

    Design Automation Conference, 2012

    With increasing complexity of designs, and with and more IP blocks being integrated to form SoCs, comes the need of verifying their numerous configurations. Different power modes, performance optimizations, memory accesses and management, concurrent and passive modes will require the different components in the verification environment at the System level to function differently. The reference implementation of the base classes as specified in the UVM provides a configuration mechanism to allow…

    With increasing complexity of designs, and with and more IP blocks being integrated to form SoCs, comes the need of verifying their numerous configurations. Different power modes, performance optimizations, memory accesses and management, concurrent and passive modes will require the different components in the verification environment at the System level to function differently. The reference implementation of the base classes as specified in the UVM provides a configuration mechanism to allow integrators to configure an environment and access and retrieve attributes across the testbench effectively. This paper demonstrates how we leveraged this mechanism to efficiently tackle complex SOC verification challenges for increased verification throughput.

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  • Chef’s Special – An Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IP

    DVCON, 2012

    With the increasingly competitive time to market of a SOC, early
    closure of verification has started to gain a lot of momentum in the
    design and verification community. As a result, based on widely used
    and emerging protocols, standards-compliant third-party Verification
    IPs are rapidly being adopted to accelerate the development of a
    complete verification environment. However, for the adoption of
    Verification IPs, there are challenges pertaining to the integration…

    With the increasingly competitive time to market of a SOC, early
    closure of verification has started to gain a lot of momentum in the
    design and verification community. As a result, based on widely used
    and emerging protocols, standards-compliant third-party Verification
    IPs are rapidly being adopted to accelerate the development of a
    complete verification environment. However, for the adoption of
    Verification IPs, there are challenges pertaining to the integration,
    the protocol specific intricacies, the underlying complexity of the
    code, and the mechanism to create user-specific tests and
    inefficiently debugging the stimulus and responses. Some of the
    standard VIPs provide test suites to reduce the effort of the
    verification engineer to code protocol specific tests. Typically, such a
    test suite would be generic in nature and will not necessarily cater to
    different flavors required by the user for DUT specific scenarios.
    There have been efforts in the past from vendors and semiconductor
    organizations alike to have an intuitive user interface for creating
    tests but those have not been very successful for different reasons.
    With the UVM Methodology, we will see how some of these
    challenges are mitigated. UVM1.0, which brings together the best
    practices and techniques across existing methodologies and the ones
    proposed by verification engineers across semiconductor
    organizations, now enables verification engineers and VIP providers
    to create highly configurable and dynamic environments. Using the
    example of the usage of a HDMI UVM VIP, this paper discusses
    how the relevant features in the UVM methodology can be
    leveraged to come up with a semi-automated mechanism of creating
    user specific tests over a third party VIP without having to be very
    well acquainted with the VIP infrastructure and the underlying
    protocol.

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  • Using the Interoperability Layer and Automation to Deliver a PCIe UVM VIP: A Successful Case Study

    Design Automation Conference, 2011 Proceedings

    The VMM-UVM interoperability library includes a collection of adapters and utilities that enable easy and flexible reuse of existing IP in both UVM and VMM environments. While both UVM and VMM are self-consistent and provide guidelines and technology to ensure reusability, trying to use a VMM VIP in a UVM testbench (or vice-versa) exposes some of the different philosophies they hold. There are trade-offs in reusing an existing VIP block in a new environment that is based on a different…

    The VMM-UVM interoperability library includes a collection of adapters and utilities that enable easy and flexible reuse of existing IP in both UVM and VMM environments. While both UVM and VMM are self-consistent and provide guidelines and technology to ensure reusability, trying to use a VMM VIP in a UVM testbench (or vice-versa) exposes some of the different philosophies they hold. There are trade-offs in reusing an existing VIP block in a new environment that is based on a different methodology library. Hence, to transform and package an industry proven VIP in such a way so that it leaves no traces of the base methodology requires going beyond Accellera’s interoperability ideology and and needs the adoption of some additional novel techniques. Though the usage of the Interoperability layer and additional techniques bring down the development time of a VIP in a new methodology substantially, vendors and developers would want to shorten this further through intelligent automation. In this paper, we taking the example of the industry proven DesignWare PCIe VMM VIP, and then, as we enumerates the steps that are required to transform it into a completely UVM compliant VIP, we highlight and elaborate on the various steps that were automated. It is important that the automation should enable the adoption of the transformation mechanism across multiple VIP’s. It proposes the idea of creating utilities to generate the wrapper implementation with minimal manual intervention.

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  • An Innovative Methodology for Verifying Mixed-signal Components

    DVCON 2011

    The traditional verification approach used in the analog world still lacks some key aspects that have been efficiently deployed to digital verification for years.
    SPICE-based analog verification environments are usually hard to reuse at System on Chip (SoC) level, difficult to control and do barely bring the required simulation performances.
    By leveraging from the well-proven VMM and UVM methodologies, the main scope of AMS-TESTBENCH is to provide analog designers and verification…

    The traditional verification approach used in the analog world still lacks some key aspects that have been efficiently deployed to digital verification for years.
    SPICE-based analog verification environments are usually hard to reuse at System on Chip (SoC) level, difficult to control and do barely bring the required simulation performances.
    By leveraging from the well-proven VMM and UVM methodologies, the main scope of AMS-TESTBENCH is to provide analog designers and verification engineers with a methodology that allows them to,
    • Introduce analog verification planning
    • Introduce constraint-random verification for driving analog nodes
    • Model analog stimulus as shaped transaction-based bus functional models
    • Integrate reference models with various abstraction level
    • Sample analog nodes to monitor incoming traffic
    • Introduce assertions on analog nodes
    • Introduce analog code coverage and functional coverage
    • Introduce regression management
    In conjunction to elaborating on above features, this paper describes a scalable and reusable methodology for verifying analog IPs. Reuse is made possible by correct modeling of verification models that can be stitched into the SoC.
    These models can be implemented with HDL or Verilog-AMS. This depends upon the required accuracy.
    This paper is a case study that explains the various aspects of this methodology that can be applied to VMM/ UVM, from verification planning to testbench implementation and coverage collection.

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  • From the Magician’s Hat: Developing a Multi-methodology PCIe Gen2 VIP

    DVCON 2011

    By using the examples of a PCIe Gen2 Synopsys DW VIP, this paper describes beyond the usage of the interoperability guidelines to not only show how a VMM VIP can be reused easily in an UVM environment but also demonstrates different novel techniques to completely transform the VIP into UVM using the VMM/UVM interoperability kit.

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