Verilog Ethernet components for FPGA implementation

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Open source FPGA-based NIC and platform for in-network compute

HDL libraries and projects

A small, light weight, RISC CPU soft core

32-bit Superscalar RISC-V CPU

3-stage RV32IMACZb* processor with debug

Various HDL (Verilog) IP Cores

RISC-V Formal Verification Framework

A DDR3 memory controller in Verilog for various FPGAs

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

ao486 port for MiSTer

Open source implementation of a x86 processor

Mega Drive/Genesis core written in Verilog

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

USB3 PIPE interface for Xilinx 7-Series

SystemVerilog synthesis tool

iCESugar series FPGA dev board

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

OpenXuantie - OpenE906 Core

i8080 precise replica in Verilog, based on reverse engineering of real die

IceChips is a library of all common discrete logic devices in Verilog

MIPSfpga+ allows loading programs via UART and has a switchable clock

Plugins for Yosys developed as part of the F4PGA project.

IBM PC Compatible SoC for a commercially available FPGA board

Open source FPGA-based NIC and platform for in-network compute

SDR Micron USB receiver

Circuits and hardware security modules formally verified with Knox 🔐