An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

high-performance RTL simulator

A dynamic verification library for Chisel.

A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Ty…